1. Field of the Invention
The present invention relates to a sampling clock adjusting method for generating a digital image signal using an analog image signal. The present invention also relates to an interface circuit for adjusting a sampling clock.
2. Description of the Related Art
Recently, digital display devices, such as a liquid crystal display and the like have been commonly used. For example, liquid crystal displays have become widely used instead of CRT (Cathode Ray Tube) displays and the like, as the display of computers.
In the case where a digital display device is used instead of an analog display device, an analog image signal should be converted to a digital image signal by sampling the analog image signal at predetermined intervals.
Since a device for generating an image signal generates an analog image signal by using an internal video clock, the level of the image signal changes according to the cycle of this video clock. Due to this, at the time of sampling an analog image signal, the sampling needs to be conducted according to a cycle which is the same as the cycle of the video clock. Further, if the sampling is conducted in an area where the level of the image signal is unstable, a noise might occur in the image to be displayed. Due to this, the sampling of the image signal needs to be conducted in an area where the level of the image signal is stable.
FIG. 10 is a block diagram showing one example of the interface circuit for generating a signal for sampling (sampling clock).
The interface circuit receives an analog image signal 101, a horizontal synchronizing signal 105 and a vertical synchronizing signal 109 supplied from an image signal output device (not shown), such as a computer etc., then, the interface circuit outputs the image signal 101, a regenerative horizontal synchronizing signal 106 and a sampling clock 108 to a digital display device 9.
As shown in FIG. 10, the interface circuit comprises a PLL (Phase Lock Loop) circuit 4, an MPU (Micro Processing Unit) 5 and a delay circuit 6.
As shown in FIG. 11, the PLL circuit 4 comprises a phase detector 21, a LPF (Low Pass Filter) 22, a VCO (Voltage Controlled Oscillator) 23 and a frequency divider 24.
The PLL circuit 4 generates the regenerative horizontal synchronizing signal 106 having a frequency F equal to that of the horizontal synchronizing signal 105 and a base clock 107 having a frequency Nxc2x7F which is N times as large as that of the horizontal synchronizing signal 105, from the horizontal synchronizing signal 105.
The regenerative horizontal synchronizing signal 106 is supplied from the PLL circuit 4 directly to the display device 9. The base clock 107 is supplied to the display device 9 as the sampling clock 108 after the phase thereof is delayed by the delay circuit 6.
The display device 9 samples the image signal 101 by using the regenerative horizontal synchronizing signal 106 and the sampling clock 108 which are supplied from the interface circuit, and converts the analog image signal into a digital image signal Then, the display device 9 displays a predetermined image with the digital image signal.
In the case where the image is not displayed desirably as a result of the interference of a noise and the like, the frequency and phase of the sampling clock 108 are adjusted by adjusting the dividing value of the frequency divider 24, and the delay amount of the delay circuit 6. Specifically, the frequency of the sampling clock 108 is set equal to the frequency of the video clock in the device for generating the image signal 101, and the phase of the sampling clock 108 is adjusted so that the image signal 101 can be sampled in an area where the level of the image signal 101 is stable.
In the case where the interface circuit having the structure shown in FIG. 10 is used, the dividing value of the frequency divider 24 and the delay amount of the delay circuit 6 are manually adjusted. Specifically, a operator of the display device 9 operates predetermined buttons and dials while watching the image displayed on the display device 9. Due to this, signals indicating the dividing value and the delay amount, respectively, are input in the MPU 5. The MPU 5 adjusts the frequency and phase of the sampling clock 108 by setting the dividing value of the frequency divider 24 and the delay amount of the delay circuit 6 in accordance with the input signals.
However, manual adjustment of the dividing value and the delay amount is troublesome and requires a high level of skill and experience. Therefore, an interface circuit which automatically adjusts the dividing value and the delay amount has been proposed.
FIG. 12 is a block diagram showing one example of an interface circuit which automatically adjusts the frequency and phase of the sampling clock 108.
As shown in FIG. 12, the interface circuit which automatically adjusts the sampling clock 108 comprises a clamping circuit 1, a D/A converter 2, a comparator 3, and a measuring circuit 8 in addition to the structure of the interface circuit shown in FIG. 10.
The analog image signal 101 supplied from the image signal output device is generally a signal having an amplitude of 0.7 volt and does not contain any direct-current component. The clamping circuit 1 clamps the image signal 101 at a reference potential by adding a predetermined direct current voltage to the image signal 101, and outputs the image signal 101 as an image signal 102 to the comparator 3.
The comparator 3 determines whether or not there are predetermined data, based on the level of the image signal 102. Specifically, the comparator 3 determines whether or not there are predetermined data in accordance with whether the level of the image signal 102 is higher or lower than the level of the reference voltage 103 supplied from the MPU 5 via the D/A converter 2. Then, the comparator 3 outputs the data existence signal 104 representing the determination result into the measuring circuit 8.
As described above, the PLL circuit 4 generates the regenerative horizontal synchronizing signal 106 and the base clock 107 from the horizontal synchronizing signal 105. The regenerative horizontal synchronizing signal 106 is supplied from the PLL circuit 4 directly to the measuring circuit 8 and the display device 9. The base clock 107 is supplied from the PLL circuit 4 to the measuring circuit 8 and the display device 9 as the sampling clock 108 after the phase thereof is delayed by the delay circuit 6.
The measuring circuit 8 counts numbers of pulses of the sampling clock 108 supplied from the delay circuit 6, using the data existence signal 104 supplied from the comparator 3 and the regenerative horizontal synchronizing signal 106 supplied from the PLL circuit 4.
Specifically, as shown in FIG. 13, the measuring circuit 2 counts a number HDmin of pulses of the sampling clock 108 and a number HDmax of pulses of the sampling clock 108 during every one horizontal synchronization period (scanning period) which is a period since one fall until the next fall of the regenerative horizontal synchronizing signal 106.
The number HDmin is a number of pulses which are counted since the first fall of the regenerative horizontal synchronizing signal 106 until the first rise of the data existence signal 104 during the scanning period. The number HDmax is a number of pulses which are counted since the first fall of the regenerative horizontal synchronizing signal 106 and the final fall of the data existence signal 104.
Then, the measuring circuit 8 outputs measurement result signal 111 indicating the respective numbers HDmin and HDmax, one after another into the MPU 5.
The MPU 5 previously stores a program for adjusting the frequency and phase of the sampling clock 108, information regarding resolutions of analog image signals, and the like.
First, the MPU 5 adjusts the frequency of the sampling clock 108, using the measurement result signals 111 supplied one after another from the measuring circuit 8.
Specifically, the MPU 5 obtains the numbers of pulses HDmin and HDmax from the measurement result signals 111 and stores the obtained numbers of pulses. However, the MPU 5 stores the minimum number among the numbers HDmin and the maximum number among the numbers HDmax all of which were obtained during one vertical synchronization period (field period) since one rise until the next rise of the vertical synchronizing signal 109.
The difference between the minimum number HDmin and the maximum number HDmax during one vertical synchronization period corresponds to the number of pixels arranged on each horizontal line of an image shown by the analog image signal 101, i.e. horizontal resolution of the analog image signal 101. The horizontal resolution can be derived from the horizontal synchronizing signal 105 and vertical synchronizing signal 109. The MPU 5 derives the horizontal resolution from the horizontal synchronizing signal 105 and vertical synchronizing signal 109 and calculates the difference of the numbers (HDmaxxe2x88x92HDmin) after one vertical synchronization period. The MPU 5 determines whether or not the calculated difference is equal to the derived horizontal resolution.
When determined that the difference of the numbers is equal to the horizontal resolution of the analog image signal 101, the MPU 5 determines that the frequency of the sampling clock 108 is an adequate value.
On the other hand, when determined that the difference of the numbers is not equal to the horizontal resolution of the analog image signal 101, the MPU 5 determines that the frequency of the sampling clock 108 is not the adequate value. The MPU 5 adds +1 or xe2x88x921 to the dividing value of the frequency divider 24 which is included in the PLL circuit 4. In such a way, the MPU 5 sets the difference of the numbers (HDmaxxe2x88x92HDmin) to a value equal to the horizontal resolution.
After adjusting the frequency of the sampling clock 108 as described above, the MPU 5 adjusts the phase of the sampling clock 108 so that the image signal 102 can be sampled in an area where the level of the image signal 102 is stable.
Specifically, as shown in FIG. 14, by changing the delay amount of the delay circuit 6, the MPU 5 controls a changing point of the sampling clock 108 and a changing point of the data existence signal 104 into a condition wherein both of the changing points coincide with each other (hereinafter, referred to as the xe2x80x9cfirst conditionxe2x80x9d). After this, by further changing the delay amount of the delay circuit 6, the MPU 5 changes the phase of the sampling clock 108 by 360 degrees, that is, by one pulse (this condition is referred to as the xe2x80x9csecond conditionxe2x80x9d).
In the case where the phase of the sampling clock 108 is set into the middle of the phase in the first condition and the phase in the second condition, the image signal 102 can be sampled in an area where the level of the image signal 102 is stable. Accordingly, with a delay amount TDa of the delay circuit 6 in the first condition and a delay amount TDb of the delay circuit 6 in the second condition, the MPU 5 calculates a delay amount ((TDa+TDb)/2) which provides the most adequate phase of the sampling clock 108, and sets the delay amount of the delay circuit 6 to the calculated delay amount.
As described above, the MPU 5 adjusts the frequency and phase of the sampling clock 108.
However, the interface circuit having the structure shown in FIG. 12 may not adjust the sampling clock 108 correctly.
For example, as shown in FIG. 13, in the case where the changing point of the sampling clock 108 coincides with the changing point of the data existence signal 104 or with the changing point of the regenerative horizontal synchronizing signal 106, the measuring circuit 8 can not obtain the number of pulses HDmin or HDmax correctly. In this case, the difference (HDmaxxe2x88x92HDmin) of the numbers of pulses is incorrect. Therefore, the MPU 5 can not adjust the frequency of the sampling clock 108 correctly.
Since the numbers of pulses can not be counted correctly, at the time of changing the phase of the sampling clock 108 by one pulse as shown in FIG. 14, the MPU 5 can not determine whether or not the phase has been changed precisely by one pulse.
As described above, the interface circuit shown in FIG. 12 may not adjust the frequency and phase of the sampling clock 108 correctly. As a result, an image may not be displayed with good looks.
Accordingly, it is an object of this invention to provide a method for adjusting a sampling clock for displaying a beautiful image.
It is another object of this invention to provide an interface circuit for generating a sampling clock for displaying a beautiful image.
It is another object of this invention to provide a method for adjusting a sampling clock correctly.
It is another object of this invention to provide an interface circuit for adjusting a sampling clock correctly.
To achieve the above objects, the sampling clock adjusting method according to the first aspect of this invention comprises:
counting a number of pulses of a sampling clock for sampling an analog image signal and a number of pulses of an adjustment clock having a frequency equal to a frequency of the sampling clock and a phase different from a phase of the sampling clock, for a predetermined time period;
determining whether or not the number of pulses of the sampling clock has been counted correctly, by comparing the counted number of pulses of the sampling clock and the counted number of pulses of the adjustment clock; and
adjusting the frequency and phase of the sampling clock, in a case where it is determined that the number of pulses of the sampling clock has been counted correctly.
According to this invention, a beautiful image can be displayed.
The determining whether or not the number of pulses of the sampling clock has been counted correctly may include determining whether or not the number of pulses of the sampling clock has been counted correctly by determining whether or not the number of pulses of the sampling clock coincides with the number of pulses of the adjustment clock within a range of an error.
The sampling clock adjusting method may further comprise controlling the number of pulses of the sampling clock to coincide with the number of pulses of the adjustment clock within the range of the error by changing the phase of the sampling clock or the phase of the adjustment clock, in a case where it is determined that the number of pulses of the sampling clock has not been counted correctly.
The counting may comprise counting the numbers of pulses of the sampling clock and adjustment clock, respectively, during a time period since a change in a level of a horizontal synchronizing signal supplied together with the analog image signal until a change in a level of a data existence signal indicating whether or not the analog image signal includes predetermined data.
The determining whether or not the number of pulses of the sampling clock has been counted correctly may include determining whether or not the number of pulses of the sampling clock has been counted correctly by determining whether or not a difference between the number of pulses of the sampling clock and the number of pulses of the adjustment clock is equal to or lower than 1 pulse.
The sampling clock adjusting method may further comprise:
generating a base clock by changing a frequency of the horizontal synchronizing signal; and
generating the sampling clock and the adjustment clock by delaying a phase of the base clock by different delay amounts, respectively.
The adjusting the frequency and phase of the sampling clock may include:
deriving a horizontal resolution of the analog image signal from a vertical synchronizing signal, supplied together with the analog image signal, and the horizontal synchronizing signal;
counting a number HDmin of pulses of the sampling clock during a time period since a change in the horizontal synchronzing signal until a first change in the data existence signal, and a number HDmax of pulses of the sampling clock during a time period since the change in the horizontal synchronizing signal until a final change in the data existence signal within a range of one scanning period;
determining whether or not a difference in the numbers HDmax and HDmin(HDmaxxe2x88x92HDmin) corresponds to the horizontal resolution; and
adjusting the frequency of the sampling clock in a case where it is determined that the difference in the numbers of pulses HDmax and HDmin does not coincide with the horizontal resolution.
The generating the base clock may include changing the frequency of the horizontal synchronizing signal with using a phase lock loop circuit which includes a frequency divider.
The adjusting the frequency of the sampling clock may include adjusting the frequency of the sampling clock by cbarging a dividing value of the frequency divider.
The adjusting the frequency of the sampling clock may include deriving the changed dividing value from an equation (1).
(the changed dividing value)=(the horizontal resolution)/(the difference between the numbers HDmax and HDmin)xc3x97(the current dividing value)xe2x80x83xe2x80x83(1)
The interface circuit according to the second aspect of this invention comprises:
a first counter which counts a number of pulses of a sampling clock for sampling an analog image signal and a number of pulses of an adjustment clock having a frequency equal to a frequency of the sampling clock and a phase different from a phase of the sampling clock, for a predetermined time period;
a first determination unit which determines whether or not the number of pulses of the sampling clock has been counted correctly, by comparing the counted number of pulses of the sampling clock and the counted number of pulses of the adjustment clock; and
a sampling clock adjustment unit which adjusts the frequency and phase of the sampling clock in a case where said first determination unit determines that the number of pulses of the sampling clock has been counted correctly.
The first determination unit may determine whether or not the number of pulses of the sampling clock has been counted correctly by determining whether or not the number of pulses of the sampling clock coincides with the number of pulses of the adjustment clock within a range of an error.
The interface circuit may further comprise a phase changing unit which controls the number of pulses of the sampling clock to coincide with the number of pulses of the adjustment clock within the range of the error by changing the phase of the sampling clock or the phase of the adjustment clock, in a case where the first determination unit determines that the number of pulses of the sampling clock has not been counted correctly.
The first counter may count the numbers of pulses of the sampling clock and the adjustment clock, respectively, during a time period since a change in a level of a horizontal synchronizing signal supplied together with the analog image signal until a change in a level of a data existence signal indicating whether or not the analog image signal includes predetermined data.
The first determination unit may determine whether or not the number of pulses of the sampling clock has been counted correctly by determining whether or not a difference between the number of pulses of the sampling clock and the number of pulses of the adjustment clock is equal to or lower than 1 pulse.
The interface circuit may further comprise:
a base clock generating unit for generating a base clock by changing a frequency of the horizontal synchronizing signal; and
a phase delaying unit for generating the sampling clock and the adjustment clock by delaying a phase of the base clock by different delay amounts, respectively.
The sampling clock adjustment unit may include:
a resolution specifying unit which derives a horizontal resolution of the analog image signal from a vertical synchronizing signal, supplied together with the analog image signal, and the horizontal synchronizing signal;
a second counter which counts the number HDmin of pulses of the sampling clock during a time period since a change in the horizontal synchronizing signal until a first change in the data existence signal, and the number HDmax of pulses of the sampling clock during a time period from the change in the horizontal synchronizing signal until a final change in the data existence signal within a range of one scanning period;
a second determination unit which determines whether or not a difference in the numbers HDmax and HDmin (HDmaxxe2x88x92HDmin) corresponds to the horizontal resolution; and
a frequency adjustment unit which adjusts the frequency of the sampling clock in a case where the second determination unit determines that the difference in the numbers of pulses HDmax and HDmin does not coincide with the horizontal resolution.
The base clock generating unit may include a phase lock loop circuit which has a frequency divider.
The frequency adjustment unit may adjust the frequency of the sampling clock by changing a dividing value of the frequency divider.
The frequency adjustment unit may derive the changed dividing value from an equation (2).
(the changed dividing value)=(the horizontal resolution value)/(the difference between the numbers HDmax and HDmin )xc3x97(the current dividing value)xe2x80x83xe2x80x83(2)